1. Field of the Invention
The present invention relates to a semiconductor device provided with a memory voltage monitoring circuit monitoring whether a power supply voltage is below a memory contents holding voltage or not.
2. Description of the Related Art
According to a semiconductor device such as an LSI, a range of the assurance voltage of a memory circuit in a state having no access is generally larger than a circuit in which an operation is continuously repeated by an internal clock. Thus, some LSI provides a memory contents holding voltage range separately from the operation voltage range. Moreover, there is proposed an LSI comprising a memory voltage monitoring circuit for monitoring a power supply voltage so as not to depart from the memory contents holding voltage range in the purpose of improving the reliability of the data of the memory circuit.
Hereinafter, a description will be made of a semiconductor device comprising a conventional memory voltage monitoring circuit disclosed in Japanese Unexamined Patent Publication No. 7-36574 with reference to FIG. 7. Referring to FIG. 7, reference character B designates a semiconductor device, reference numeral 1 designates an internal circuit existing in the semiconductor device B such as a CPU (Central Processing Unit) or a RAM (Random Access Memory), reference numeral 2 designates a memory voltage monitoring circuit that monitors a power supply voltage VDD supplied to the semiconductor device B and outputs a low voltage detection signal SL when the power supply voltage VDD drops below a memory contents holding voltage V1, reference numeral 3 designates a low voltage detection signal holding circuit that temporally holds the low voltage detection signal from the memory voltage monitoring circuit 2 and outputs it to the internal circuit 1 as a low voltage detection holding signal SH, reference numeral 4 designates a reset circuit that receives an external reset signal R1 and generates and outputs a reset signal R2, and reference numeral 11 designates an operation voltage monitoring circuit such as a reset IC that is provided outside the semiconductor device B and monitors the power supply voltage VDD and outputs an external reset signal R1 when the power supply voltage VDD drops below an operation voltage V2 (V2>V1).
The memory voltage monitoring circuit 2 starts the operation in response to an inversion signal S5 of an operation no-permission signal S4 outputted from the internal circuit 1. The low voltage detection signal holding circuit 3 is cleared by a clear signal CR from the internal circuit 1.
According to the above conventional technique, since the memory voltage monitoring circuit 2 is constantly in an operating state after a power supply is turned on, the power consumption of the memory voltage monitoring circuit 2 is increased. In view of reducing the power consumption, the power consumed by the memory voltage monitoring circuit cannot be ignored and therefore, the memory voltage monitoring circuit is not mounted in a semiconductor device that features reduction in power consumption in many cases.
Moreover, even in a semiconductor device provided with the memory voltage monitoring circuit, it needs control by the memory voltage monitoring circuit when the operation mode is transmitted to a low power consumption mode, which requires a complicated programming process. Meanwhile, when the memory voltage monitoring circuit stops the monitoring operation, the voltage detection itself cannot be implemented at the time of executing the low power consumption mode.